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Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
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The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified, and wherein FIG. 10 is a flowchart illustrating an erase method according to an exemplary embodiment of the inventive concept. 11 is a block diagram illustrating an erase voltage generator in FIG. 12 according to another exemplary embodiment of the inventive concept. 15 is a graph illustrating an erase voltage output from a ramping circuit in FIG. 18 is a graph illustrating a waveform of an erase voltage when the erase voltage gradually increases. 19 is a diagram illustrating threshold voltages of string and ground selection transistors when performing an erase operation using an erase voltage in FIG. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.
1 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept. 2 is a diagram illustrating a memory cell array in FIG. 1 according to an exemplary embodiment of the inventive concept. 4 is a perspective view taken along a line I-I′ of a memory block in FIG. 8 is a diagram illustrating a voltage condition of a memory block at an erase operation according to the prior art. 9 is a diagram illustrating a cell string biased according to the voltage condition in FIG. 12 according to still another exemplary embodiment of the inventive concept. 16 is a graph illustrating a waveform of an erase voltage when the erase voltage is a square wave, according to the prior art. 17 is a diagram illustrating threshold voltages of string and ground selection transistors when performing an erase operation using the erase voltage of FIG. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that, although the terms first, second, third etc.
Integrated circuit memory devices according to embodiments of the invention include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. The control circuit is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval.
This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).The erase voltage generator may include a totem-pole arrangement of transistors, which are configured as diodes.According to additional embodiments of the invention, the erase voltage generator includes a charge pump and a ramping circuit, which is configured to generate the erase voltage by sequentially tapping intermediate nodes of the totem-pole arrangement of transistors having different voltage levels.It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features.1 according to an exemplary embodiment of the inventive concept. 3 according to an exemplary embodiment of the inventive concept. 5 is a cross-sectional view taken along a line of a memory block in FIG. 7 is a circuit diagram illustrating an equivalent circuit of a memory block described in FIGS. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms.